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dm2m36sj6/dm2m32sj6 multibank edo 2mbx36/2mbx32 enhanced dram simm product specification ?1996 enhanced memory systems inc., 1850 ramtron drive, colorado springs, co 80921 telephone (800) 545-dram; fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2119-000 the information contained herein is subject to change without notice. enhanced reserves the right to change or discontinue this product without notice. features n 16kbyte sram cache memory for 12ns random reads within eight active pages (multibank cache) n fast dram array for 30ns access to any new page n write posting register for 12ns random writes and burst writes within a page (hit or miss) n 2kbyte wide dram to sram bus for 113.6 gigabytes/sec cache fill n on-chip cache hit/miss comparators maintain cache coherency on writes n hidden precharge and refresh cycles n extended 64ms refresh period for low standby power n standard cmos/ttl compatible i/o levels and +5 or 3.3v volt supply n compatibility with jedec 2m x 36 dram simm configuration allows performance upgrade in system n multibank extended data output (edo) for faster system operation n low power, self refresh option n industrial temperature range option description the enhanced memory systems multibank edo 8mb edram simm module provides a single memory module solution for the main memory or local memory of fast pcs, workstations, servers, and other high performance systems. due to its fast 12ns cache row register, the edram memory module supports zero-wait-state burst read operations at up to 83mhz bus rates in a non-interleave configuration and >132mhz bus rates with a two-way interleave configuration. on-chip write posting and fast page mode operation supports 12ns write and burst write operations. on a cache miss, the fast dram array reloads the 2kbyte cache over a 2kbyte-wide bus in 18ns for an effective bandwidth of 113.6 gbytes/sec. this means very low latency and fewer wait states on a cache miss than a non- integrated cache/dram solution. the jedec compatible 72-bit simm configuration allows a single memory controller to be designed to support either jedec slow drams or high speed edrams to provide a simple upgrade path to higher system performance. architecture the dm2m36sj6 achieves 2mb x 36 density by mounting 18 1mb x 4 edrams, packaged in 28-pin plastic soj packages, on both sides of the multi-layer substrate. sixteen dm2242 and two dm2252 devices provide data and parity storage. the dm2m32sj6 contains 16 dm2242 devices for data only. the edram memory module architecture is very similar to a standard 8mb dram module with the addition of an integrated cache and on- chip control which allows it to operate much like an edo dram. the edrams sram cache is integrated into the dram array as tightly coupled row registers. each edram bank has a total of four independent dram memory banks each with its own sram row register. memory reads always occur from the cache row register of one of these banks as specified by row address bits a 2 and a 9 (bank select). when the internal comparator detects that the row address matches the last row read from any of the four dram banks (page hit), the sram is accessed and data is available on the output pins in 12ns from the column address input. subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. when the row address does not match the last row read from any of the last four dram banks (page miss), the new dram row is accessed and loaded into the appropriate sram row register and data is available on the output pins all within 30ns from row enable. subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. since reads occur from the sram cache, the dram precharge can occur during burst reads. this eliminates the precharge time delay suffered by other drams and sdrams when accessing a new page. the edram has an independent on-chip refresh counter and dedicated refresh control pin to allow the dram array to be refreshed concurrently with cache read operations (hidden refresh). memory writes are posted to the input data latch and directed to the dram array. during a write hit, the on-chip address comparator activates a parallel write path to the sram cache to maintain /cal a 0-10 w/r /f v v sense amps & column write select column decoder row add latch cc ss 4 - 512 x 36 cache pages (row registers) x 2 memory array 2048 x 512 x 36 x 2 /g /s /we dq 0-35 0, 1 column add latch 8-bit comp 8 last row read add latch i/o control and data latches refresh counter row decoder row add and refresh control 0-3,p /re 0,2,3 a 0-8 a 0-9 c 1-18 functional diagram enhanced memory systems inc.
coherency . random or page mode writes can be posted 5ns after column address and data are available. the edram allows 12ns page mode cycle time for both write hits and write misses. memory writes do not affect the contents of the cache row register except during a cache hit. by integrating the sram cache as row registers in the dram array and keeping the on-chip control simple, the edram is able to provide superior performance over standard slow drams. by eliminating the need for srams and cache controllers, system cost, board space, and power can all be reduced. functional description the edram is designed to provide optimum memory performance with high speed microprocessors. as a result, it is possible to perform simultaneous operations to the dram and sram cache sections of the edram. this feature allows the edram to hide precharge and refresh operation during sram cache reads and maximize sram cache hit rate by maintaining valid cache contents during write operations even if data is written to another memory page. these new functions, in conjunction with the faster basic dram and cache speeds of the edram, minimize processor wait states. edram basic operating modes the edram operating modes are specified in the table. hit and miss t er minology in this datasheet, ?it?and ?iss?always refer to a hit or miss to any of the four pages of data contained in the sram cache row registers. there are four cache row registers, one for each of the four banks of dram. these registers are specified by the bank select row address bits a 2 and a 9 . the contents of these cache row registers is always equal to the last row that was read from each of the four internal dram banks (as modified by any write hit data). bank selection the 8mbyte edram simm has two separate 4mbyte banks on one module. the two banks share common data, multiplexed address, and control signals with the exception of /re and /s. bank selection is performed by using both /re and /s to select a bank. the use of /s to select a bank is required on the 8mbyte simm because /g is common between the two banks. if /s is grounded (i.e., not used to control bank selection), an output buffer conflict between the two banks will occur when /g is enabled. it is also necessary to clock the /re signal for each bank separately since clocking /re with /s disabled is not allowed (see ?nallowed mode?description). 2-96 bank 3 bank 2 bank 1 cal row address latch column address latch last row read address latch + 9-bit compare bank 0 1 of 4 selector (0,0) (0,1) (1,0) (1,1) d 0-35 bank 0 bank 1 bank 2 bank 3 ca 0-8 ca 0-8 ra 2 , ra 9 a 0-10 ra 0-10 data-out latch g s q 0-35 1mb array 1mb array 1mb array 1mb array 512 x 36 cache 512 x 36 cache 512 x 36 cache 512 x 36 cache data-in latch four bank cache ar chitectur e (one of t wo banks)
2-97 dram read hit a dram read request is initiated by clocking /re with w/r low and /f and /cal high. the edram will compare the new row address to the last row read address latch for the bank specified by row address a 2, 9 (lrr; an 9-bit latch loaded on each /re active read cycle). if the row address matches the lrr, the requested data is already in the sram cache and no dram memory reference is initiated. the data specified by the column address is available at the output pins at the greater of times t rac1, t ac, t gqv , and t asc + t cl v . since no dram activity is initiated, /re can be brought high after time t re1 , and a shorter precharge time, t rp1 , is required. it is possible to access additional sram cache locations by providing new column addresses to the multiplex address inputs. new data is available at the output at time t asc + t cl v after each column address change. dram read miss a dram read request is initiated by clocking /re with w/r low and /f . the edram will compare the new row address to the lrr address latch for the bank specified by row address bits a 2, 9 (lrr: 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address does not match the lrr, the requested data is not in sram cache and a new row must be fetched from the dram. the edram will load the new row data into the sram cache and update the lrr latch. the data at the specified column address is available at the output pins at the greater of times t rac, t ac, t gqv , and t asc + t cl v . it is possible to bring /re high after time t re since the new row data is safely latched into sram cache. this allows the edram to precharge the dram array while data is accessed from sram cache. it is possible to access additional sram cache locations by providing new column addresses to the multiplex address inputs. new data is available at the output at time t asc + t cl v after each column address change. dram w rite hit a dram write request is initiated by clocking /re while w/r, w/e, and /f are high. the edram will compare the new row address to the lrr address latch for the bank specified by row address bits a 2, 9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address matches the lrr, the edram will write data to both the dram page in the appropriate bank and its corresponding sram cache simultaneously to maintain coherency . the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . with /g enabled and /we disabled, it is possible to perform cache read operations while the /re is activated in write hit mode. this allows read-modify-write, write- verify , or random read-write sequences within the page with 12ns cycle times (the first read cannot complete until after time t rac2 ). at the end of a write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . it is possible to perform cache reads concurrently with precharge. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, the /cal input can be used as a byte write select in multi-chip systems. if /cal is not clocked on a write sequence, the memory will perform a /re only refresh to the selected row and data will remain unmodified. dram w rite miss a dram write request is initiated by clocking /re while w/r, w/e, and /f are high. the edram will compare the new row address to the lrr address latch for the bank specified for row address bits a 2, 9 (lrr : a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address does not match any of the lrrs, the edram will write data to the dram page in the appropriate bank and the contents of the current cache is not modified. the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . during a write miss sequence, cache reads are inhibited and the output buffers are disabled (independently of /g) until time t wrr after /re goes high. at the end of a write sequence (after /cal and /we function /s low power standby h /re w/r /f a 0-10 comment h x x x low power self refresh option h x h x internal refresh x x l x read miss l l h row 1 lrr dram row to cache write hit l h h row = lrr write to dram and cache, reads enabled write miss l h h row 1 lrr write to dram, cache not updated, reads disabled cache reads enabled standby current standby current, internal refresh clock read hit l l h /cal h l x h h h h /we h unallowed mode h l x h x unallowed mode (except -l option) x x h x x h h x row = lrr no dram reference, data in cache h = high; l = low; x = don? care; = high-to-low transition; lrr = last row read edram basic operating modes
2-98 are brought high and t re is satisfied), /re can be brought high to precharge the memory . it is possible to perform cache reads concurrently with the precharge. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, /cal can be used as a byte write select in multi-chip systems. if /cal is not clocked on a write sequence, the memory will perform a /re only refresh to the selected row and data will remain unmodified. /re inactive operation it is possible to read data from the sram cache without clocking /re. this option is desirable when the external control logic is capable of fast hit/miss comparison. in this case, the controller can avoid the time required to perform row/column multiplexing on hit cycles. this capability also allows the edram to perform cache read operations during precharge and refresh cycles to minimize wait states. it is only necessary to select /s for the selected bank (/s 0 or /s 1 ) and /g and provide the appropriate column address to read data. the row address of the sram cache accessed without clocking /re will be specified by the lrr address latch loaded during the last /re active read cycle. t o perform a cache read, /cal is clocked to latch the column address. the cache data is valid at time t cl v after the column address is setup to /cal. w rite-per -bit operation the dm2m36sj edram simm provides a write-per -bit capability to selectively modify individual parity bits (dq 8,17,26,35 ) for byte write operations. the parity devices (dm2252) are selected via /cal p . data bits do not require or support write-per -bit capability . byte write selection to non-parity bits is accomplished via /cal 0-3 . the bits to be written are determined by a bit mask data word which is placed on the parity i/o data pins prior to clocking /re. the logic one bits in the mask data select the bits to be written. as soon as the mask is latched by /re, the mask data is removed and write data can be placed on the databus. the mask is only specified on the /re transition. during page mode burst write operations, the same mask is used for all write operations. inter nal refr esh if /f is active (low) on the assertion of /re, an internal refresh cycle is executed. this cycle refreshes the row address supplied by an internal refresh counter . this counter is incremented at the end of the cycle in preparation for the next /f refresh cycle. at least 1,024 /f cycles must be executed every 64ms. /f refresh cycles can be hidden because cache memory can be read under column address control throughout the entire /f cycle. /f cycles are the only active cycles during which /s can be disabled. /cal befor e /re refr esh (?cas befor e /ras? /cal before /re refresh, a special case of internal refresh, is discussed in the ?educed pin count operation?section below . /re only refr esh operation although /f refresh using the internal refresh counter is the recommended method of edram refresh, it is possible to perform an /re only refresh using an externally supplied row address. /re refresh is performed by executing a write cycle (w/r and /f are high) where /cal is not clocked. this is necessary so that the current cache contents and lrr are not modified by the refresh operation. all combinations of addresses a 0-9 must be sequenced every 64ms refresh period. a 10 does not need to be cycled. read refresh cycles are not allowed because a dram refresh cycle does not occur when a read refresh address matches the lrr address latch. +3.3 v olt power supply operation if the +3.3 volt power supply option is specified, the edram will operate from a +3.3 volt + 0.3 volt power supply and all inputs and outputs will have l vttl/l vcmos compatible signal levels. the +3.3 volt edram will not accept input levels which exceed the power supply voltage. if mixed i/o levels are expected in your system, please specify the +5 volt version of the edram. low power mode the edram enters its low power mode when /s is high. in this mode, the internal dram circuitry is powered down to reduce standby current. low power , self-refr esh option when the low power , self refresh mode option is specified when ordering the edram, the edram enters this mode when /re is clocked while /s, w/r, /f , and /we are high; and /cal is low . in this mode, the power is turned off to all i/o pins except /re to minimize chip power , and an on-board refresh clock is enabled to perform self- refresh cycles using the on-board refresh counter . the edram remains in this low power mode until /re is brought high again to terminate the mode. the edram /re input must remain high for t rp2 following exit from self-refresh mode to allow any on-going internal refresh to terminate prior to the next memory operation. initialization cycles a minimum of eight /re active initialization cycle (read, write or refresh) are required before normal operations is guaranteed. following these start-up cycles, two read cycles to different row addresses must be performed for each of the four internal banks of dram to initialize the internal cache logic. row address bits a 2 and a 9 define the four internal dram banks. /re must be high for 300ns prior to initialization. unallowed mode read, write, or /re only operations must not be initiated to unselected memory banks by clocking /re when /s is high. reduced pin count operation it is possible to simplify the interface to the 8mbyte simm to reduce the number of control lines. /re0 and /re2 could be tied together externally to provide a single row enable for bank 0. w/r and /g can be tied together if reads are not performed during write hit cycles. this external wiring simplifies the interface without any performance impact. pin descriptions /re 0,2,3 ?row enable this input is used to initiate dram read and write operations and latch a row address as well as the states of w/r and /f . it is not necessary to clock /re to read data from the edram sram row registers. on read operations, /re can be brought high as soon as data is loaded into cache to allow early precharge. /re to bank 0 and bank 1 must be clocked separately and only clocked during dram operations to the selected bank.
2-99 pin no. function 1 gnd interconnect (component pin) organization c (8,21,28) ground 2 3 4 u1,10 (26) byte 1 i/o 2 5 6 u1,10 (25) byte 1 i/o 3 7 8 u1,10 (24) byte 1 i/o 4 9 10 +5/3.3 v c (7,14,22) 11 +5/3.3 v c (7,14,22) 12 c (1) address 13 14 15 16 17 18 c (9) address 19 20 u3,12 (27) 21 u4,13 (24) 22 u3,12 (26) 23 u4,13 (25) 24 u3,12 (25) 25 u4,13 (26) byte 3 i/o 7 26 u3,12 (24) byte 1 i/o 8 27 u4,13 (27) byte 3 i/o 8 28 c (10) address 29 gnd c (8,21,28) ground 30 +5/3.3 v c (7,14,22) 31 c (11) address 32 c (13) address 33 u10-18 (6) bank 1 row enable 34 u2,4,5,7,8 (6) 35 36 a 9 bank 0 row enable (bytes 3,4, parity) 37 u5,14 (25) parity i/o for byte 2 38 u5,14 (24) 39 gnd c (8,21,28) 40 u1,3,10,12 (16) byte 1 column address latch 41 u2,4,11,13 (16) byte 3 column address latch 42 u7,8,16,17 (16) byte 4 column address latch 43 u6,9,15,18 (16) byte 2 column address latch 44 u1,3,6,9 (6) bank 0 row enable (bytes 1,2) 45 u10-18 (19) chip select bank 1 46 u5,14 (16) parity column address latch 47 48 c (20) write enable 49 u6,15 (27) byte 2 i/o 1 50 u7,16 (27) byte 4 i/o 1 51 u6,15 (26) byte 2 i/o 2 52 u7,16 (26) byte 4 i/o 2 53 u6,15 (25) byte 2 i/o 3 54 u7,16 (25) byte 4 i/o 3 55 u6,15 (24) 56 u7,16 (24) byte 4 i/o 4 57 u9,18 (24) byte 2 i/o 5 58 u8,17 (24) byte 4 i/o 5 59 +5/3.3 v c (7,14,22) 60 u8,17 (26) byte 4 i/o 6 61 u9,18 (25) byte 2 i/o 6 62 u8,17 (25) byte 4 i/o 7 63 u9,18 (26) byte 2 i/o 7 64 u8,17 (24) byte 4 i/o 8 65 u9,18 (27) byte 2 i/o 8 66 +5/3.3 v c (7,14,22) 67 c (23) 68 c (18) 69 /s u1-9 (19) 70 pd signal gnd 71 gnd c (8,21,28) 72 /g c (8,21,28) parity i/o for byte 4 /we gnd /f output enable refresh mode control chip select bank 0 presence detect ground c = common to all memory chips, u1 = chip 1, etc. pin no. function interconnect (component pin) organization byte 1 i/o 5 byte 3 i/o 5 byte 1 i/o 6 byte 1 i/o 7 byte 3 i/o 6 ground byte 2 i/o 4 ground u1,10 (27) byte 1 i/o 1 u2,11 (24) byte 3 i/o 1 u2,11 (25) byte 3 i/o 2 u2,11 (26) byte 3 i/o 3 u2,11 (27) byte 3 i/o 4 v cc a 0 c (2) address a 1 c (12) address a 2 c (3) a 3 address c (4) address a 4 c (5) address a 5 c (15) address v cc u5,14 (27) parity i/o for byte 3 u5,14 (26) parity i/o for byte 1 v cc a 6 a 7 a 8 v cc a 10 v cc dq 0 dq 18 dq 1 dq 19 dq 2 dq 20 dq 3 dq 21 dq 4 dq 22 dq 5 dq 23 dq 6 dq 24 dq 7 dq 25 /re 2 dq * 26 dq * 8 dq 16 dq 34 dq 15 dq 33 dq 14 dq 32 dq 31 dq 13 dq 30 dq 12 dq 29 dq 11 dq 28 dq 10 dq 27 dq 9 /cal * p /re 0 /cal 1 /cal 3 /cal 2 /cal 0 dq * 35 dq * 17 c (17) w/r mode control w/r *no connect for dm2m32sj /s 1 0 /re 3 pinout
2-100 byte 1 byte 2 byte 3 byte 4 dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2252j 1mb x 4 edram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq 0 1 2 3 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq 4 5 6 7 8 dq0 dq1 dq2 dq3 /cal 27 26 25 24 9 10 11 12 dq0 dq1 dq2 dq3 /cal 27 26 25 24 14 15 16 17 dq0 dq1 dq2 dq3 /cal 27 26 25 24 19 20 21 dq0 dq1 dq2 dq3 /cal 27 26 25 24 23 24 25 26 dq0 dq1 dq2 dq3 /cal 27 26 25 24 27 28 29 30 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq 31 dq 22 dq 18 dq 13 32 33 34 dq 35 dq0 dq1 dq2 dq3 /cal 27 26 25 24 vcc vcc vcc vss vss vss parity 7 14 22 8 21 28 16 16 16 16 16 16 16 16 16 1 2 12 3 4 5 9 10 11 13 15 17 20 18 19 23 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 /re0 /re2 w/r /we /f /s0 /g /cal0 /cal1 vcc vcc vcc vcc vcc vss vss vss vss vss pd +5v (3.3v) 10 11 30 59 66 1 29 39 71 72 70 40 43 68 69 67 48 47 12 13 14 15 16 17 18 28 31 32 19 44 34 dq35 dq34 dq33 dq32 dq31 dq30 dq29 dq28 dq27 dq26 dq25 dq24 dq23 dq22 dq21 dq20 dq19 dq18 dq17 dq16 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 38 64 62 60 58 56 54 52 50 35 27 25 23 21 9 7 5 3 37 65 63 61 57 55 53 51 49 36 26 24 22 20 8 6 4 2 j1 edge connecter +5v (3.3v) /cal2 41 /cal3 42 /calp 46 /cal0 /cal1 /cal2 /cal3 /calp /re /re /re /re /re /re /re /re c1 c2 c3 c4 c5 c6 c7 c8 c9 /re * *dm2212 is not present on the dm2m32sj. 6 6 6 6 6 6 6 6 6 u1 u3 u6 u9 u2 u4 u7 u8 u5 inter connect diagram ?bank 0 (components mounted on fr ont side)
2-101 byte 1 byte 2 byte 3 byte 4 dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2242j 1mb x 4 edram dm2252j 1mb x 4 edram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 dq0 dq1 dq2 dq3 /cal 27 26 25 24 vcc vcc vcc vss vss vss 7 14 22 8 21 28 16 16 16 16 16 16 16 16 16 1 2 12 3 4 5 9 10 11 13 15 17 20 18 19 23 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 /re3 w/r /we /f /s1 /g /cal0 /cal1 vcc vcc vcc vcc vcc vss vss vss vss vss pd +5v (3.3v) 10 11 30 59 66 1 29 39 71 72 70 40 43 68 45 67 48 47 12 13 14 15 16 17 18 28 31 32 19 33 dq35 dq34 dq33 dq32 dq31 dq30 dq29 dq28 dq27 dq26 dq25 dq24 dq23 dq22 dq21 dq20 dq19 dq18 dq17 dq16 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 38 64 62 60 58 56 54 52 50 35 27 25 23 21 9 7 5 3 37 65 63 61 57 55 53 51 49 36 26 24 22 20 8 6 4 2 j1 edge connecter +5v (3.3v) /cal2 41 /cal3 42 /calp 46 /cal0 /cal1 /cal2 /cal3 /calp /re /re /re /re /re /re /re /re c10 c11 c12 c13 c14 c15 c16 c17 c18 /re *dm2212 is not present on the dm2m32sj. 6 6 6 6 6 6 6 6 6 parity * u10 u12 u15 u18 u11 u13 u16 u17 u14 dq 0 1 2 3 dq 4 5 6 7 8 9 10 11 12 14 15 16 17 19 20 21 23 24 25 26 27 28 29 30 dq 31 dq 22 dq 18 dq 13 32 33 34 dq 35 inter connect diagram ?bank 1 (components mounted on back side)
2-102 /cal 0-3,p ?column addr ess latch this input is used to latch the column address and in combination with /we to trigger write operations. when /cal is high, the column address latch is transparent. when /cal is low , the column address is closed and the output of the latch contains the address present while /cal was high. it also controls the operation of the output data latch. data is latched while /cal is high and the latch is transparent when /cal is low . w/r ?w rite/read this input along with /f specifies the type of dram operation initiated on the low going edge of /re. when /f is high, w/r specifies either a write (logic high) or read operation (logic low). /f ?refr esh this input will initiate a dram refresh operation using the internal refresh counter as an address source when it is low on the low going edge of /re. /we ?w rite enable this input controls the latching of write data on the input data pins. a write operation is initiated when both /cal and /we are low . /g ?output enable this input controls the gating of read data to the output data pin during read operations. /s 0,1 ?chip select this input is used to power up the i/o and clock circuitry . when /s is high, the edram remains in its low power mode. /s must be used for bank selection on the 8mbyte simm. /s must remain active throughout any read or write operation. with the exception of /f refresh cycles, /re should never be clocked when /s is inactive. dq 0-35 ?data input/output these bidirectional data pins are used to read and write data to the edram. on the dm2252 write-per -bit memory , these pins are also used to specify the bit mask used during write operations. a 0-10 ?multiplex addr ess these inputs are used to specify the row and column addresses of the edram data. the 11-bit row address is latched on the falling edge of /re. the 9-bit column address can be specified at any other time to select read data from the sram cache or to specify the write column address during write cycles. v cc power supply these inputs are connected to the +5 or 3.3 volt power supply . v ss gr ound these inputs are connected to the power supply ground connection. ambient operating temperature (t a ) description ratings output voltage (v out ) power supply voltage (v cc ) storage temperature (t s ) static discharge voltage (per mil-std-883 method 3015) short circuit o/p current (i out ) - 1 ~ 7v - 1 ~ 7v input voltage (v in ) - 1 ~ 7v -40 ~ +85? -55 ~ 150? class 1 50ma* 3.3v option rating - .5 ~ 4.6v - .5 ~ 4.6v - .5 ~ 4.6v -40 ~ +85? -55 ~ 150? class 1 20ma* absolute maximum ratings (beyond which permanent damage could result) * one output at a time per device; short duration description max* pins input capacitance input capacitance i/o capacitance 165/180pf 16pf 130/136pf a 0-10 w/r, /we, /f dq 0-35 input capacitance 52/55pf /cal 0-3 input capacitance 32pf /cal p input capacitance 62/64pf /g input capacitance 52pf /re 0 input capacitance 55/65pf /re 2 input capacitance 92/96pf /re 3 input capacitance 97/100pf /s 0 , /s 1 capacitance * dm2m32sj6/dm2m36sj6, respectively
r = 828 r = 1178 w (3.3 volt) 1 1 5ns v gnd 5.0v (3.3v option) w (5 volt) output c = 50pf l r = 295 2 load circuit input waveforms w (5 volt) r = 868 2 w (3.3 volt) 5ns il v il v ih v ih 2-103 symbol parameters 3.3v option min max min max test conditions v cc supply voltage 4.75v 5.25v all voltages referenced to v ss v v i i v ih il i(l) o(l) oh v ol ov v 6.5v, all other pins not under test = 0v in ov v , ov v 5.5v out i = - 5ma (-2ma for 3.3v option) v +0.3v out cc v -0.3v ss i = 4.2ma (2ma for 3.3v option) 6.5v 0.8v 180? 0.4v 0.4v 180? 2.4v -1.0v -180? -180? 2.4v 3.0 3.6 0.8v 90? 90? 2.0 -90? -90? 2.4v input high voltage input low voltage input leakage current output leakage current output high level output low level in out electrical characteristics t a = 0 - 70 c, (commer cial), -40 ~ 85 c (industrial) symbol operating current -15 max test condition i cc1 random read /re, /cal, /g and addresses cycling: t = t minimum c cc cc ss /re, /cal, /we and addresses cycling: t = t minimum c /cal, /we and addresses cycling: t = t minimum 920ma 720ma 1.6ma 840ma fast page mode read static column read self-refresh (-l option) random write fast page mode write pc 1440ma i cc2 i cc3 i cc4 i cc5 0-10 i cc7 1200ma 33mhz typ 520ma 440ma 1.6ma 400ma 880ma 1080ma c notes 2, 3 2, 4 2, 4 2, 3 2, 4 /cal, /g and addresses cycling: t = t minimum pc pc /g and addresses cycling: t = t minimum sc sc c pc 3 -12 max 1440ma 920ma 720ma 1.6ma all control inputs stable v - 0.2v 3 < /s, /f, w/r, /we and a at v -0.2v, /re and /cal at v + 0.2v, i/o option 16ma standby i cc6 16ma 16ma 1200ma 840ma see "estimating edram operating power" application note average typical operating current i cct 240ma 1 (1) operating cur r ent ?dm2m32sj symbol operating current -15 max test condition i cc1 random read /re, /cal, /g and addresses cycling: t = t minimum c cc cc ss /re, /cal, /we and addresses cycling: t = t minimum c /cal, /we and addresses cycling: t = t minimum 1035ma 810ma 1.8ma 945ma fast page mode read static column read self-refresh (-l option) random write fast page mode write pc 1620ma i cc2 i cc3 i cc4 i cc5 0-10 i cc7 1350ma 33mhz typ 585ma 495ma 1.8ma 450ma 990ma 1215ma c notes 2, 3 2, 4 2, 4 2, 3 2, 4 /cal, /g and addresses cycling: t = t minimum pc pc /g and addresses cycling: t = t minimum sc sc c pc 3 -12 max 2025ma 1305ma 990ma 1.8ma all control inputs stable v - 0.2v, outputs driven 3 < /s, /f, w/r, /we and a at v -0.2v, /re and /cal at v +0.2v, i/o option 18ma standby i cc6 18ma 18ma 1710ma 1215ma see "estimating edram operating power" application note average typical operating current i cct 270ma 1 (1) (1) ?3mhz typ?refers to worst case i cc expected in a system operating with a 33mhz memory bus. see power applications note for further details. this parameter is not 100% tested or guaranteed. (2) i cc is dependent on cycle rates and is measured with cmos levels and the outputs op en. (3) i cc is measured with a maximum of one address change while /re = v il . ( 4) i cc is measured with a maximum of one address change while /cal = v ih . operating cur r ent ?dm2m36sj ac t est load and w avefor ms v in t iming reference point at v il and v ih
2-104 symbol description t ac (1) t asc t asr t c t c1 t cae t cah t ch t cqv t crp t cwl t dh t ds t gqv (1) t gqx (2,3) column address access time column address setup time row enable cycle time row enable cycle time, cache hit (row=lrr), read cycle only row address setup time column address latch active time column address hold time column address latch high time (latch transparent) column address latch high to data invalid column address latch setup time to row enable /we low to /cal inactive data input hold time data input setup time output enable access time output enable to output drive time 5 5 55 20 5 5 5 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min max units 12 5 0 15 0 5 t aqx column address change to output data invalid ns 5 t ach column address valid to /cal inactive (write cycle) ns 12 5 min max -12 -15 t nrs t pc t rac (1) t rac1 (1) t rah output turn-off delay from output disabled (/g - ) /cal, /g, w/r, and /we setup time for /re-only refresh column address latch cycle time row address hold time row enable access time, on a cache miss t nrh /cal, /g, w/r, and /we hold time for /re-only refresh t msu /f and w/r mode select setup time t mh /f and w/r mode select hold time ns 0 5 ns 0 ns 5 ns 0 ns 5 ns 12 ns 30 ns t gqz (4,5) t rac2 (1,6) row enable access time for a cache write hit ns 30 1 t chr /cal inactive lead time to /re inactive (write cycles only) -2 ns t chw column address latch high to write enable low (multiple writes) 0 ns row enable access time, on a cache hit (limit becomes t ac ) 15 ns t dmh mask hold time from row enable (write-per-bit) 5 ns t dms mask setup time to row enable (write-per-bit) ns t re row enable active time ns 30 100000 1 5 5 65 25 5 5 5 0 5 15 6 0 15 t cqh column address latch low to data invalid ns 0 5 t clv column address latch high to data valid ns 7 7 0 5 5 t aci column address ns 12 15 15 5 0 5 0 5 0 5 15 35 35 1.5 -2 0 17 5 35 100000 1.5 switching characteristics v cc = 5v 5% (+5 v olt option), vcc = 3.3v 0.3v (+3.3 v olt option), c l = 50pf, t a = 0 to 70 c (commercial), -40 to 85 c (industrial)
2-105 symbol description t rgx t rp (7) t rp1 t rrh t rsh t output enable don't care from row enable (write, cache miss), o/p hi z row precharge time row precharge time, cache hit (row=lrr) read cycle read hold time from row enable (write only) last write address latch to end of write row enable to column address latch low for second write 9 20 8 0 ns ns ns ns ns ns min max units 35 t rp2 row precharge time, self-refresh mode 100 ns min max t rqx1 (2,6) row enable high to output turn-on after write miss 0 ns -12 -15 12 rsw ns t rwl last write enable to end of write ns 12 t sc column address cycle time ns 12 t shr select hold from row enable ns 0 t sqv (1) chip select access time ns 12 t sqx (2,3) output turn-on from select low ns 12 0 output turn-off from chip select ns 8 0 t ssr select setup time to row enable ns 5 t t transition time (rise and fall) ns 10 1 t wc write enable cycle time ns 12 t wch column address latch low to write enable inactive time ns 5 t wi write enable inactive time ns 5 (1) v out timing reference point at 1.5v (2) parameter defines time when output is enabled (sourcing or sinking current) and is not referenced to v oh or v ol (3) minimum specification is referenced from v ih and maximum specification is referenced from v il on input control signal (4) parameter defines time when output achieves open-circuit condition and is no t referenced to v oh or v ol (5) minimum specification is referenced from v il and maximum specification is referenced from v ih on input control signal (6) access parameter applies when /cal has not been asserted prior to t rac2 (7) for back-to-back /f refreshes, t rp = 40ns. for non-consecutive /f refreshes, t rp = 25ns and 32ns respectively. (8) for write-per-bit devices, t whr is limited by data input setup time, t ds t wp t wrp t wrr write enable active time write enable setup time to row enable write to read recovery (following write miss) 16 ns ns ns 5 data turn-off from write enable low ns t wqx (2,5) data output turn-on from write enable high ns 0 t wqv (1) data valid from write enable high ns 12 5 12 0 12 t re1 t ref row enable active time, cache hit (row=lrr) read cycle refresh period ms 64 8 ns t whr (7) write enable hold after /re ns 0 t sqz (4,5) t wqz (3,4) 12 10 25 10 0 40 100 0 15 15 15 0 15 15 0 10 0 5 10 1 15 5 5 18 5 0 15 5 15 0 15 64 10 0 15 switching characteristics (continued) v cc = 5v 5% (+5 v olt option), vcc = 3.3v 0.3v (+3.3 v olt option), c l = 50pf, t a = 0 to 70 c (commercial), -40 to 85 c (industrial)
2-106 /re /f w/r a 0-10 /cal 0-3, p /g /s 0,1 t cah column 1 column 2 t asc t cah t ch t cae t pc t cqv t ac t cqh t clv t clv data 1 open data 2 t gqz t gqx t gqv t ac t sqz t sqv t sqx row t asc dq 0-35 0,2,3 /we don? care or indeterminate notes: 1. data accessed during /re inactive read is from the row address specifi ed during the last /re active read cycle. 2. latched data becomes invalid when /s is inactive. t aci /re inactive cache read hit (edo mode)
2-107 /re 0,2,3 t c1 row /f w/r a 0-10 /cal /g /s 0,1 t re1 t msu t mh t rp1 t asr t rah t cah column 1 column 2 t crp t asc t cah t ch t cqv t cae t pc t ac t rac1 t cqh t clv t clv data 1 open data 2 t gqz t gqx t gqv t ac t ssr t sqz t shr t mh t msu row t asc dq 0-35 /we don? care or indeterminate note: 1. latched data becomes invalid when /s is inactive. t aci 0-3, p /re active cache read hit (edo mode)
2-108 /re 0,2,3 /f w/r a 0-10 /cal 0-3, p /g /s 0,1 t msu t c t re t rp t mh t mh t rah t msu t asr t crp t cah t asc t asc t cah t ch t cae t pc t cqv t rac t cqh t clv t clv t ac open t ac t gqz t ssr t gqx t gqv t shr t sqz row column 1 column 2 row data 1 data 2 dq 0-35 /we don? care or indeterminate note: 1. latched data becomes invalid when /s is inactive. t aci /re active cache read miss (edo mode)
2-109 /re 0,2,3 /f w/r /cal 0-3,p /we /g t re /s 0,1 column 1 t msu t msu t asr t mh t mh t rah t rsw column 2 row column n cache (column n) open t crp t cah t asc t cwl t cae t cwl t rsh t cae t wrp t wp t rrh t cae t cah t asc t wch t wch t pc t wp t rwl t dh t dh t ds t ds t ac t wrr t gqx t rqx1 t gqv t ssr dq 0-35 a 0-8 data 1 data 2 t clv t ach t ach t ch t whr t wi t wc t chw t rp t chr a 0-8 a 0-8 a 0-10 don? care or indeterminate notes: 1. 2. parity bits dq 8,17,26,35 must have mask provided at falling edge of /re. /g becomes a don? care after t rgx during a write miss. a 0-10 t cah burst w rite (hit or miss) followed by /re inactive cache reads
2-110 /re 0,2,3 /f w/r a 0-10 /cal 0-3, p /we /g t re /s 0,1 column 1 t msu t msu t asr t mh t mh t rah column 2 row column 3 t wrp t clv t asc t gqx t ssr dq 0-35 a 0-8 read data t whr t c t rp don? care or indeterminate notes: 1. 2. if column address 1 equals column address 2, then a read-modify-write cycle is p erformed. parity bits dq 8,17,26,35 must have mask provided at falling edge of /re. t ac t crp t cae t ach t asc t rsh t cah t wch t rrh t clv t chr t cqv t cae t wp t cwl write data read data t rac2 t ac t ds t rwl t gqv t gqz t dh t gqz t wqx t gqv t wqv t asc t cah page read/w rite during w rite hit cycle
2-111 /re 0,2,3 /cal p w/r a 0-10 /we /f t re /s 0,1 t rah t msu t asr t mh t ssr dq 0-35 t rp t rsh t cae row column t asc t cah t chr t cwl mask data t t dmh dms t rwl t wch t wrp t ds t dh t wp t rrh t msu t mh t shr t ach t whr don? care or indeterminate notes: 1. 2. 3. data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit wri te. write-per-bit cycle valid only for dm2m36sj6. write-per-bit waveform applies to parity bits only (dq 8,17,26,35 ). w rite-per -bit cycle (/g = high)
2-112 t c /f t re t rp t asr t rah row t nrs t nrh t ssr t shr t msu t mh /re 0,2,3 a 0-10 /s 0,1 don? care or indeterminate notes: 1. all binary combinations of a 0-9 must be refreshed every 64ms interval. a 10 does not have to be cycled, but must remain valid during row address setup and hold times. 2. /re refresh is write cycle with no /cal active cycle. / cal 0-3,p , /we, /g, w/r /re 0, 2,3 /f t re t msu t mh don? care or indeterminate notes: 1. 2. during /f refresh cycles, the status of w/r, /we, a 0-10 , /cal, /s, and /g is a don? care. /re inactive cache reads may be performed in parallel with /f refresh cycles. t rp /f refr esh cycle /re-only refr esh
2-113 /f, w/r, /we, /s t rp2 t msu t mh t msu t mh /re don? care or indeterminate notes: 1. edram self refreshes as long as /re remains low. (low power self-refresh parts only). 2. when using the low power self refresh mode the following operations must be perf ormed: if row addresses are being refreshed in an evenly distributed manner over the refresh interval using /f refresh cycles, then at least one /f refresh cycle must be performed immediately after exit from the low power self refresh mode. if row addresses are being refreshed in any other manner (/f burst or /re distributed or burst), then all rows must be refresh immediately before entry to and immediately after exit from the low power self refresh. a 0-10 0,2,3 /cal low power self-refr esh mode option
2-114 dm2m36sj 6- 12i dynamic memory memory depth (megabits) i/o width (including parity) packaging system access time from cache in nanoseconds 12ns 15ns temperature range no designator = 0 to 70 o c (commercial) i = -40 to 85 o c (industrial) l = 0 to 70 o c, low power self-refresh configuration 6 = 5 volt, multibank edo 7 = 3.3 volt, multibank edo j = 300 mil, plastic soj memory module configuration s = simm 32 = 32 bits 36 = 36 bits 2m par t numbering system the information contained herein is subject to change without notice. enhanced memory systems inc. assumes no responsibility fo r the use of any circuitry other than circuitry embodied in an enhanced product, nor does it convey or imply any license under patent or other rights. 4.245 (107.82) 4.255 (108.08) 3.984 (101.19) 0.133 (3.38) 0.075 (1.90) 0.085 (2.16) 0.050 (1.27) 1.750 (44.45) 2.125 (53.98) 3.750 (95.25) 0.250 (6.35) 0.040 (1.02) 0.042 (1.07) 0.060 (1.52) 0.064 (1.63) 0.250 (6.35) 0.062 (1.57) rad. 0.245 (6.22) 0.255 (6.48) 0.400 (10.16) 0.945 (24.00) 0.955 (24.26) 0.123 (3.12) 0.127 (3.22) 0.100 (2.54) u1 1 72 u2 u3 u4 u5 u6 u7 u8 u9 c1 c2 c3 c4 c5 c6 c7 c8 c9 inches (mm) 0.225 (5.72) rad. 0.010 (.254) 0.047 (1.19) 0.054 (1.37) 0.365 (9.28) u1-u4, u6-u9, u10-u13, u15-u17 u5, u14 c1-c18 socket enhanced dm2242j-xx, 1m x 4 edrams, 300 mil soj enhanced dm2252j-xx, 1m x 4 edram with write-per-bit (not present on dm2m32sj) 0.22? chip capacitors amp 822030-3 or equivalent double side mounting mechanical data 72 pin simm module

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